TLK100_11 Datasheet, PDF (58/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
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8.4.9 BIST Byte Count Register (BISBCR)
This register gives the total number of bytes received by the PRBS checker.
BIT
BIT NAME
15:0 prbs_byte_cnt
Table 8-22. BIST Count Register (BISBCR), address 0x0071
DEFAULT
0, RO
DESCRIPTION
Holds number of total bytes that received by the PRBS checker. Value in this register is locked
when write is done to register 0x0072 bit[0] or bit[1]. When PRBS Count Mode set to zero,
count stops on 0xFFFF (see register 0x0016)
8.4.10 BIST Error Count Register (BISECR)
This register gives the total number of error bytes that was received by the PRBS checker.
Table 8-23. BIST Error Count Register (BISECR), address 0x0072
BIT
BIT NAME
15:8 Reserved
7:0 prbs_err_cnt
DEFAULT
0, RO
0, RO
DESCRIPTION
Ignore on read
Holds number of erroneous bytes received by the PRBS checker. Value in this register is
locked when write is done to bit[0] or bit[1] (see below).
When PRBS Count Mode set to zero, count stops on 0xFF (see register 0x0016)
Notes:
Writing bit 0 generates a lock signal for the PRBS counters
Writing bit 1 generates a lock and clear signal for the PRBS counters
8.4.11 BIST Packet Length Register (BISPLR)
This register allows programming the length of the PRBS packet in bytes.
Table 8-24. BIST Packet Length Register (BISPLR), address 0x007B
BIT
BIT NAME
DEFAULT
15:0 Cfg_pkt_len_prbs 0X5DC,RW Length of PRBS packets in bytes
DESCRIPTION
8.4.12 BIST Inter Packet Gap Register (BISIPGR)
This register allows programming the inter packet gap, in bytes, between the PRBS packets.
Table 8-25. BIST Inter Packet Gap Register (BISIPGR), address 0x007C
BIT
BIT NAME
15:0 Cfg_ipg_len
DEFAULT
DESCRIPTION
0X7D,RW Inter-packet gap (in bytes) between PRBS packets
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