TLK100_11 Datasheet, PDF (75/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
www.ti.com
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
Table 9-9. 100BASE-TX Receive Packet Latency Timing
PARAMETER
t₁
Carrier Sense ON Delay⁽²⁾
t₂
Receive Data Latency
TEST CONDITIONS⁽¹⁾
100 Mb/s Normal mode
100 Mb/s Normal mode
MIN TYP MAX UNIT
13.6
bits ⁽³⁾
18.4
bits
(1) PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
(2) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
(3) 1 bit time = 10 ns in 100 Mb/s mode
PMD Input Pair IDLE
(J/K)
Data
t₁
CRS
t₂
RXD[3:0]
RX_DV
RX_ER
Figure 9-9. 100BASE-TX Receive Packet Latency Timing
T0346-01
Table 9-10. 100BASE-TX Receive Packet Deassertion Timing
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
t₁
Carrier Sense OFF Delay⁽¹⁾
100 Mb/s Normal mode
13.6
bits ⁽²⁾
(1) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
(2) 1 bit time = 10 ns in 100 Mb/s mode
PMD Input Pair DATA
(T/R)
IDLE
t₁
CRS
Figure 9-10. 100BASE-TX Receive Packet Deassertion Timing
T0347-01
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Electrical Specifications
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