TLK100_11 Datasheet, PDF (63/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
www.ti.com
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
8.5.8 TDR Control Register (TDRCR)
This register allows configuring the TDR modes.
Table 8-37. TDR Control Register (TDRCR), address 0x0C01
BIT
15:11
10
9
8:6
NAME
Reserved
cfg_tdr_tx_mode
Reserved
cfg_soft_avr_cycles
5:3 cfg_post_cmp_size
2:0 cfg_pre_cmp_size
DEFAULT
0x02,RO
0x1,RW
0,RW
0x7,RW
0x4,RW
0x3,RW
FUNCTION
Ignore on read
1 – Enable TDR TX transmission mode
Reserved
Number of averaging cycles:
0x0 – TDR disabled.
0x1 – 1 TDR cycle (no averaging).
0x2 – 2 TDR cycles.
0x3 – 4 TDR cycles.
0x4 – 8 TDR cycles.
0x5 – 16 TDR cycles.
0x6 – 32 TDR cycles.
0x7 – 64 TDR cycles.
Number of forward samples for peak detection comparison.
Number of backward samples for peak detection comparison.
8.5.9 TDR Clock Cycles Register (TDRLCR)
This register allows configuring the number of clock cycles in a pattern TDR test.
Table 8-38. TDR Clock Cycles Register (TDRLCR), address 0x0C02
BIT
NAME
15:8 Reserved
7:0 cfg_ptrn_cycle_time
DEFAULT
0,RO
0xFF,RW
FUNCTION
Ignore on read
Number of clock cycles in a TDR pattern test.
8.5.10 TDR Low Threshold Register (TDRLT1)
This register allows configuring the threshold for finding the peaks of the reflected signal in the TDR test.
Table 8-39. TDR Low Threshold Register (TDRLT1), address 0x0C03
BIT
NAME
15 Reserved
14:8 cfg_ptrn_low_th_1
7
Reserved
6:0 cfg_ptrn_low_th_0
DEFAULT
0,RO
0xC,RW
0,RO
0x10,RW
FUNCTION
Ignore on read
Peak (absolute) low threshold value 1, for TX pattern.
Ignore on read
Peak (absolute) low threshold value 0, for TX pattern.
8.5.11 TDR Low Threshold Register (TDRLT2)
This register allows configuring the threshold for finding the peaks of the reflected signal in the TDR test.
Table 8-40. TDR Low Threshold Register (TDRLT2), address 0x0C04
BIT
NAME
15 Reserved
14:8 cfg_ptrn_low_th_3
7
Reserved
6:0 cfg_ptrn_low_th_2
DEFAULT
0,RO
0x7,RW
0,RO
0x9,RW
FUNCTION
Ignore on read
Peak (absolute) low threshold value 3, for TX pattern.
Ignore on read
Peak (absolute) low threshold value 2, for TX pattern.
Copyright © 2009, Texas Instruments Incorporated
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