TLK100_11 Datasheet, PDF (7/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
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2.5 JTAG Interface
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
PIN
TYPE
NAME
NO.
DESCRIPTION
JTAG_TCK
44 I, PU This pin is the test clock.This pin has a weak internal pullup.
JTAG_TDI
45 I, PU This pin is the test data input.This pin has a weak internal pullup.
JTAG_TDO
47
O This pin is the test data output.
JTAG_TMS
46 I, PU This pin selects the test mode. This pin has a weak internal pullup.
JTAG_TRST
N
48
I, PU ^{This pin is an active low asynchronous test reset. This pin has a weak internal pullup.}
2.6 Reset and Power Down
PIN
NAME
NO.
TYPE
DESCRIPTION
RESETN
This pin is an active Low reset input that initializes or re-initializes all the internal registers of the
43
I, PU TLK100. Asserting this pin low for at least 1 μs will force a reset process to occur. All jumper
options are reinitialized as well.
Register access is required for this pin to be configured either as power down or as an interrupt.
The default function of this pin is power down.
PWRDNN/INT
When this pin is configured for a power down function, an active low signal on this pin will put the
42
I, OD, PU device is power down mode.
When this pin is configured as an interrupt pin then this pin is asserted low when an interrupt
condition occurs. The pin has an open-drain output with a weak internal pull-up. Some
applications may require an external pull-up resistor.
Copyright © 2009, Texas Instruments Incorporated
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Pin Descriptions
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