TLK100_11 Datasheet, PDF (15/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
www.ti.com
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
3.3 PHY Address
The 5 PHY address inputs pins are shared with the MII_RXD[3:0] pins and COL pin as shown in
Table 3-2.
Table 3-2. PHY Address Mapping
PIN #
24
25
26
27
28
PHYAD FUNCTION
PHYAD0
PHYAD1
PHYAD2
PHYAD3
PHYAD4
RXD FUNCTION
MII_COL
MII_RXD_0
MII_RXD_1
MII_RXD_2
MII_RXD_3
Each TLK100 or port sharing an MDIO bus in a system must have a unique physical address. With 5
address input pins, the TLK100 can support PHY Address values 0 (<00000>) through 31 (<11111>). The
address-pin states are latched into an internal register at device power-up and hardware reset. Because
all the PHYAD[4:0] pins have weak internal pull-down resistors, the default setting for the PHY address is
00000 (0x00h).
See Figure 3-1 for an example of a PHYAD connection to external components. In this example, the
PHYAD configuration results in address 00010 (0x02h).
PHYAD4 = 0 PHYAD3 = 0 PHYAD2 = 0 PHYAD1 = 1 PHYAD0 = 1
2.2 kW
VCC
Figure 3-1. PHYAD Configuration Example
B0314-01
Copyright © 2009, Texas Instruments Incorporated
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Configuration
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