TLK100_11 Datasheet, PDF (71/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
www.ti.com
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
9.6 AC Specifications
Table 9-1. Power Up Timing
PARAMETER
t₁
Reset deassertion time from power up
t₂
Time from reset deassertion to the hardware
configuration pins transition to output drivers
TEST CONDITIONS
Hardware Configuration Pins are described in
the Pin Description section.
MIN TYP MAX UNIT
200
μs
46
ns
V_CC
t₁
XI Clock
Hardware
RESET_N
t₂
Dual Function Pins
Become Enabled As Outputs
Input
Figure 9-1. Power Up Timing
Output
T0338-01
NOTE
It is important to choose pull-up and/or pull-down resistors for each of the hardware
configuration pins that provide fast RC time constants in order to latch-in the proper value
prior to the pin transitioning to an output driver.
PARAMETER
t₁
RESET pulse width
Table 9-2. Reset Timing
TEST CONDITIONS
XI Clock must be stable for at min. of 1ms
during RESET pulse low time.
MIN TYP MAX UNIT
1
μs
V_CC
XI Clock
Hardware
RESET_N
t₁
Figure 9-2. Reset Timing
T0339-01
Copyright © 2009, Texas Instruments Incorporated
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