TLK100_11 Datasheet, PDF (17/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
www.ti.com
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
3.5 Loopback Functionality
The TLK100 provides several options for Loopback that test and verify various functional blocks within the
PHY. Enabling loopback mode allows in-circuit testing of the TLK100 digital and analog data path.
Generally, the TLK100 may be configured to one of the Near-end loopback modes or to the Far-end
(reverse) loopback.
3.5.1 Near-End Loopback
Near-end loopback provides the ability to loop the transmitted data back to the receiver via the digital or
analog circuitry. The point at which the signal is looped back is selected using loopback control bits with
several options being provided. Figure 3-3 shows the PHY near-end loopback functionality.
PCS Loopback
Analog Loopback
MAC/
Switch
M
I
I
PCS
Signal
Process
PHY Digital
PHY
AFE
1
2
3
XFMR
4
5
6
7
8
MII Loopback
Digital Loopback
External Loopback
Figure 3-3. Block Diagram, Near-End Loopback Mode
The Near-end Loopback mode is selected by setting the respective bit in the BIST Control Register
(BISCR), MII register address 0x16. Bits 3:0 of the BISCR register are used to set the loopback mode
according to the following:
• Bit [0]: MII Loopback
• Bit [1]: PCS Loopback (in 100BaseTX only)
• Bit [2]: Digital Loopback
• Bit [3]: Analog Loopback
While in Loopback mode the data is looped back and also transmitted onto the media. To ensure proper
operation in Analog Loopback mode 100Ω terminations should be attached to the RJ45 connector.
External Loopback can be performed while working in normal mode (Bits 3:0 of the BISCR register are
assert to 0 and on RJ45 connector pin 1 is shorted to pin 3 and pin 2 is shorted to pin 6).
To maintain the desired operating mode, Auto-Negotiation should be disabled before selecting Loopback
mode. This is not relevant for external-loopback mode.
Copyright © 2009, Texas Instruments Incorporated
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