LAN83C183 Datasheet, PDF (93/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

5.3.3 Receive Timing Characteristics
Table 5.10 shows the Receive AC timing parameters. See Figure 5.4 through Figure
5.8 for the receive timing diagrams.
Table 5.10 Receive Timing
Sym
Parameter
Min
t31
Start Of Packet To
CRS
Assert Delay
t32
End Of Packet To
130
CRS
Deassert Delay
t33
Start Of Packet To
RX_DV Assert
Delay
t34
End Of Packet To
RX_DV Deassert
Delay
t37
RX_CLK To
−8
RX_DV,
RXD, RX_ER
−80
Delay
t38
RX_CLK High
18
Time
180
t39
RX_CLK Low Time 18
180
t40
SOI Pulse
125
Minimum Width
Required for Idle
Detection
Limit
Typ
Max
200
200
700
240
240
600
240
3600
280
1000
8
80
20
22
200
600
20
22
200
600
200
Unit
Conditions
ns 100 Mbits/s, MII
ns 100 Mbits/s, FBI
ns 10 Mbits/s
ns 100 Mbits/s, MII
ns 100 Mbits/s, FBI
ns 10 Mbits/s. relative to start of SOI pulse
ns 100 Mbits/s
ns 10 Mbits/s
ns 100 Mbits/s
ns 10 Mbits/s. relative to start of SOI pulse
ns 100 Mbits/s
ns 10 Mbits/s
ns 100 Mbits/s
ns 10 Mbits/s
ns 100 Mbits/s
ns 10 Mbits/s
ns 10 Mbits/s measure TPI± from last zero
cross to 0.3V point.
SMSC DS – LAN83C183
93
Rev. 12/14/2000