LAN83C183 Datasheet, PDF (71/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

MASK_ SPD_DET
R/W 7
Interrupt Mask - 10/100 Speed Detect
MASK_SPD_DET
Bit
Meaning
1
Mask Interrupt for SPD_DET bit in register
18 (default)
0
No mask
MASK_ DPLX_DET
R/W 6
Interrupt Mask - 10/100 Duplex Detect
MASK_DPLX_DET
Bit
Meaning
1
Mask Interrupt for DPLX_DET bit in
register 18 (default)
0
No mask
FXLVL[1:0] Fiber Transmit Level Adjust
FXLVL[1:0]
Bits Adjustment
0b11 1.30
0b10 1.15
0b01 0.85
0b00 1.00
(default)
R/W [5:4]
R
Reserved
R/W [3:0]
These bits are reserved and must be remain at the default value of
0 for proper device operation
3.3.11 Reserved Register (Register 20)
The default value for this register is 0x0000.
15
8
Reserved
7
0
Reserved
R
Reserved
R/W [15:0]
These bits are reserved and must be remain at the default value of
0 for proper device operation.
SMSC DS – LAN83C183
71
Rev. 12/14/2000