LAN83C183 Datasheet, PDF (78/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

4.5 REGISTER STRUCTURE
The device has 11 16-bit registers. A map of the registers is shown in Section 3.2,
“MI Serial Port Register Summary”. See Chapter 3, Registers for a complete
description of each register.
The 11 registers consist of six registers that are defined by IEEE 802.3 specifications
(registers 0 to 5) and five registers that are unique to the device (registers 16 through
20). Table 4.1 gives a summary of the functions of each register.
Table 4.1 MI Serial Port Register Summary
Register Name
Description
0
Control Register
Stores various configuration bits
1
Status Register
Contains device capability and status output bits
2
PHY ID 1
Contain an identification code unique to the device
3
PHY ID 2
4
AutoNegotiation
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Contains bits that control the operation of the
AutoNegotiation algorithm
5
AutoNegotiation
Remote End
Capability
Contains bits that reflect the AutoNegotiation capabilities
of the link partner’s PHY
16 Configuration 1
Stores various configuration bits
17 Configuration 2
Stores various configuration bits
18 Channel Status Output Contains status
19 Mask
Contains interrupt mask bits
20 Reserved
Reserved for factory use
SMSC DS – LAN83C183
78
Rev. 12/14/2000