LAN83C183 Datasheet, PDF (30/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

The FX transmit output current level is derived from an internal reference voltage and
the external resistor on the REXT pin. The FX transmit level can be adjusted with
this resistor or it can also be adjusted with the two FX Transmit Level Adjust bits
(FXLVL[1:0]) in the MI serial port Mask register as shown in Table 1.7.
Table 1.7 FX Transmit Level Adjust
FXLVL[1:0]
Bits
11
10
01
00
Gain
1.30
1.15
0.85
1.00
1.2.9.2 RECEIVER
The FX receiver:
• Converts the differential ECL inputs on the FXI+/- pins to a digital bit stream
• Validates the data on FXI+/- with the SD/FXDISn input pin
• Enable or disables the FX interface with the SD/FXDISn pin.
The FX receiver meets all requirements defined in IEEE 802.3.
The input to the FXI+/- pins can be directly driven from a fiber optic transceiver and
first goes to a comparator. The comparator compares the input waveform against the
internal ECL threshold levels to produce a low jitter serial bit stream with internal logic
levels. The data from the comparator output is then passed to the clock and data
recovery block, provided that the signal detect input, SD/FXDISn, is asserted.
Signal Detect – The FX receiver has a signal detect input pin, SD/FXDISn, which
indicates whether the incoming data on FXI+/- is valid or not. The SD/FXDISn input
can be driven directly from an external fiber optic transceiver and meets all
requirements defined in the IEEE 802.3 specifications.
The SD/FXDISn input goes directly to a comparator. The comparator compares the
input waveform against the internal ECL threshold level to produce a digital signal
with internal logic levels. The output of the signal detect comparator then goes to the
link integrity and squelch blocks. If the SD/FXDISn input is asserted, the device is
placed in the Link Pass state and the input data on FXI+/- is determined to be valid.
If the SD/FXDISn input is deasserted, the device is placed in the Link Fail state and
the input data on FXI+/- is determined to be invalid.
The SD_THR pin adjusts the ECL trip point of the SD/FXDISn input. When the
SD_THR pin is tied to a voltage between GND and GND + 0.45V, the trip point of
the SD/FXDISn ECL input buffer is internally set to VDD − 1.3 V. When the SD_THR
pin is set to a voltage greater than GND + 0.85 V, the trip point of the SD/FXDISn
ECL input buffer is set to the voltage that is applied to the SD_THR pin. The trip level
for the SD/FXDISn input buffer must be set to VDD − 1.3 V. Having external control
of the SD/FXDISn buffer trip level with the SD_THR pin allows this trip level to be
referenced to an external supply, which facilitates connection to an external fiber
optic transceiver. If the device is to be connected to a 3.3V external fiber optic
transceiver, SD_THR must be tied to GND.
SMSC DS – LAN83C183
30
Rev. 12/14/2000