LAN83C183 Datasheet, PDF (23/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

CRS pin is continuously asserted whenever the device is in the Link Pass state.
Setting the bit automatically places the device in the FBI mode as described in the
subsection entitled “FBI Selection” on page 1-19.
1.2.5 Scrambler
100BASE-TX transmission requires scrambling to reduce the radiated emissions on
the twisted pair. The scrambler takes the NRZI encoded data from the 4B5B encoder,
scrambles it per the IEEE 802.3 specifications, and sends it to the TP transmitter. A
scrambler is not used for 10 Mbits/s operation.
1.2.5.1 SCRAMBLER BYPASS
Setting the Bypass Encoder/Decoder bit (BYP_SCR) in the MI serial port
Configuration 1 register bypasses the scrambler. When this bit is set, 5B data
bypasses the scrambler and goes directly to the 100BASE-TX transmitter.
1.2.6 Descrambler
The descrambler block shown in Figure 1.1 is used in 100BASE-TX operation. The
device descrambler takes the scrambled NRZI data from the data recovery block,
descrambles it according to IEEE 802.3 specifications, aligns the data on the correct
5B word boundaries, and sends it to the 4B5B decoder.
The algorithm for synchronization of the descrambler is the same as the algorithm
outlined in the IEEE 802.3 specification.
After the descrambler is synchronized, it maintains synchronization as long as
enough descrambled idle pattern ones are detected within a given interval. To stay
in synchronization, the descrambler needs to detect at least 25 consecutive
descrambled idle pattern ones in a 1 ms interval. If 25 consecutive descrambled idle
pattern ones are not detected within the 1 ms interval, the descrambler goes out of
synchronization and restarts the synchronization process.
If the descrambler is in the unsynchronized state, the descrambler Loss of
Synchronization Detect bit (LOSS_SYNC) is set in the MI serial port Status Output
register. The bit stays set until the descrambler achieves synchronization.
The descrambler is disabled for 10BASE-T operation.
1.2.6.1 DESCRAMBLER BYPASS
Setting the Bypass Encoder/Decoder bit (BYP_SCR) in the MI serial port
Configuration 1 register bypasses the descrambler. When this bit is set, 5B data
bypasses the descrambler and goes directly from the
100BASE-T receiver to the 4B5B decoder.
SMSC DS – LAN83C183
23
Rev. 12/14/2000