LAN83C183 Datasheet, PDF (68/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

INT_MDIO Interrupt Scheme Select
R/W 2
INT_MDIO
Bit
Meaning
1
Interrupt signaled with MDIO pulse during idle
0
Interrupt not signaled on MDIO (default)
R/J_CFG R/J Configuration Select
R/W 1
R/J_CFG
Bit
Meaning
1
RX_EN/JAMn pin is configured to be JAMn
0
RX_EN/JAMn pin is configured to be RX_EN
(default)
R
Reserved
R/W 0
This bit is reserved and must be remain at the default value of 0x0
for proper device operation.
3.3.9 Status Output Register (Register 18)
The default value for this register is 0x0080.
15
INT
LNK_FAIL LOSS_SYNC CWRD
SSD
8
ESD
RPOL
JAB
7
5
0
SPD_DET DPLX_DET
Reserved
INT
INT Bit
1
0
Interrupt Detect
R 15
Meaning
Interrupt bit(s) have changed since last read
operation
No change (default)
LNK_FAIL Link Fail Detect
LNK_FAIL Bit Meaning
1
Link not detected
0
Normal (default)
R/LT 14
LOSS_SYNCDescrambler Loss of Synchronization DetectR/LT 13
LOSS_SYNC
Bit
Meaning
1
Descrambler has lost sync
0
Normal (default)
CWRD Codeword Error
R/LT 12
CWRD Bit Meaning
1
Invalid 4B5B code detected on receive data
0
Normal (default)
SSD
Start of Stream Error
R/LT 11
SSD Bit Meaning
1
No Start of Stream Delimiter detected on
receive data
0
Normal (default)
SMSC DS – LAN83C183
68
Rev. 12/14/2000