LAN83C183 Datasheet, PDF (77/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

4.4 FRAME STRUCTURE
The structure of the serial port frame is shown in Figure 4.2 and a timing diagram is
shown in Figure 4.1. Each serial port access cycle consists of 32 bits, exclusive of
idle. The first 16 bits of the serial port cycle are always write bits and are used for
control and addressing. The last 16 bits are data that is written to or read from a data
register.
The first two bits in Figure 4.2 and Figure 4.1 are start bits (ST[1:0]) and must be
written as a 0b01 for the serial port cycle to continue. The next two bits are the READ
and WRITE bits, which determine whether a registers is being read or written. The
next five bits are the PHY device address bits (PHYAD[4:0]), and they must match
the inverted values latched from the MDA[4:0]n pins during the power on reset time
for access to continue.
The next five bits are register address select (REGAD[4:0]) bits, which select one of
the 11 registers for access. The next two bits are turnaround (TA) bits, which are not
actual register bits but provide the device extra time to switch the MDIO pin function
from a write pin to a read pin, if necessary. The final 16 bits of the MI serial port cycle
are written to or read from the specific data register that the register address bits
(REGAD[4:0]) designate. Figure 4.2 shows the MI frame structure.
Figure 4.2 MI Serial Frame Structure
IDLE ST[1:0] READ WRITE PHYAD[4:0] REGAD[4:0] TA[1:0] D[15:0]
IDLE
Idle Pattern
W
These bits are an idle pattern. The device does not
initiate an MI cycle until it detects an idle pattern of at least 32 con-
secutive ones.
ST[1:0]
Start Bits
W
When ST[1:0] = 01, a MI serial port access cycle starts.
READ
Read Select
W
When the READ bit is 1, it designates a read cycle.
WRITE
Write Select
W
When the WRITE bit is 1, it designates a write cycle.
PHYAD[4:0]
Physical Device Address
W
When the PHYAD[4:0] bits match the inverted latched value of the
MDA[3:0]n pins, the device’s MI serial port is selected for operation.
REGAD[4:0] Register Address
W
The REGAD[4:0] bits determine the specific register to access.
TA[1:0]
Turnaround Time
R/W
These bits provide some turnaround time for MDIO to allow it to
switch to a write input or read output, as needed. When READ = 1,
TA[1:0] = 0bZ0; when
WRITE = 1, TA[1:0] = 0b10.
D[15:0]
Data
R or W
These 16 bits contain data to or from one of the registers selected
with the register address bits REGAD[4:0].
SMSC DS – LAN83C183
77
Rev. 12/14/2000