LAN83C183 Datasheet, PDF (18/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

Table 1.3 4B/5B Symbol Mapping
Symbol
Name
Description
5B Code
4B Code
0
Data 0
0b11110
0b0000
1
Data 1
0b01001
0b0001
2
Data 2
0b10100
0b0010
3
Data 3
0b10101
0b0011
4
Data 4
0b01010
0b0100
5
Data 5
0b01011
0b0101
6
Data 6
0b01110
0b0110
7
Data 7
0b01111
0b0111
8
Data 8
0b10010
0b1000
9
Data 9
0b10011
0b1001
A
Data A
0b10110
0b1010
B
Data B
0b10111
0b1011
C
Data C
0b11010
0b1100
D
Data D
0b11011
0b1101
E
Data E
0b11100
0b1110
F
Data F
0b11101
0b1111
I
Idle
0b11111
0b0000
J
SSD #1
0b11000
0b0101
K
SSD #2
0b10001
0b0101
T
ESD #1
0b01101
0b0000
R
ESD #2
0b00111
0b0000
H
Halt
0b00100
Undefined
–
Invalid codes
All others¹
0b0000*
1. These 5B codes are not used. The decoder decodes these 5B codes to
4B 0000. The encoder encodes 4B 0000 to 5B 11110, as shown in symbol
Data 0.
Because the OSCIN input clock generates the TX_CLK output clock, the TXD[3:0],
TX_EN, and TX_ER signals are also clocked in on rising edges of OSCIN.
On the receive side, as long as a valid data packet is not detected, CRS and RX_DV
are deasserted and the RXD[3:0] signals are held LOW. When the start of packet is
detected, CRS and RX_DV are asserted on the falling edge of RX_CLK. The
assertion of RX_DV indicates that valid data is clocked out on RXD[3:0] on the falling
edge of the RX_CLK. The RXD[3:0] data has the same frame structure as the
TXD[3:0] data and is specified in IEEE 802.3 and shown in Figure 1.3. When the end
SMSC DS – LAN83C183
18
Rev. 12/14/2000