LAN83C183 Datasheet, PDF (16/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

1.2 BLOCK DIAGRAM DESCRIPTION
The LAN83C183 PHY device has the following main blocks:
• Oscillator and Clock
• Controller Interface
• 4B5B/Manchester Encoder/Decoder
• Scrambler/Descrambler
• Twisted-Pair Transmitters
• Fiber Transmitter
• Twisted-Pair Receivers
• Fiber Receiver
• Clock and Data Recovery
• AutoNegotiation/Link Integrity
• Descrambler
• Collision Detection
• LED Drivers
A Management Interface (MI) serial port provides access to 11 internal PHY
registers.
Figure 1.1 shows the main blocks, along with their associated signals. The following
sections describe each of the blocks in Figure 1.1. The performance of the device in
both the 10 and 100 Mbits/s modes is described.
1.2.1 Oscillator and Clock
The LAN83C183 requires a 25 MHz reference frequency for internal signal
generation. This 25 MHz reference frequency is generated with either an external 25
MHz crystal connected between OSCIN and GND or with the application of an
external 25-MHz clock to OSCIN.
The device provides either a 2.5-MHz or 25-MHz reference clock at the TX_CLK or
RX_CLK output pins for 10-MHz or 100-MHz operation, respectively.
1.2.2 Controller Interface
This section describes the controller interface operation. The LAN83C183 has two
interfaces to an external controller:
• Media Independent Interface (MII)
• Five Bit Interface (FBI)
1.2.2.1 MII INTERFACE
The device has an MII interface to an external Ethernet Media Access Controller
(MAC).
MII (100 Mbits/s) – The MII is a nibble wide packet data interface defined in IEEE
802.3 and shown in Figure 1.3. The LAN83C183 meets all the MII requirements
outlined in IEEE 802.3. The LAN83C183 can directly connect, without any external
logic, to any Ethernet controller or other device that also complies with the IEEE
802.3 MII specifications.
SMSC DS – LAN83C183
16
Rev. 12/14/2000