LAN83C183 Datasheet, PDF (38/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

1.3 START OF PACKET
This section describes start of packet operation for both the 100 Mbits/s and 10
Mbits/s modes.
1.3.1 100 Mbits/s
A unique Start of Stream Delimiter (SSD) indicates the start of packet for 100 Mbits/s
mode. The SSD pattern consists of two /J/K/ 5B symbols inserted at the beginning
of the packet in place of the first two preamble symbols, as defined in IEEE 802.3
Clause 24 and shown in Table 1.4 and Figure 1.2.
The 4B5B encoder generates the transmit SSD and inserts the /J/K/ symbols at the
beginning of the transmit data packet in place of the first two 5B symbols of the
preamble, as shown in Figure 1.2.
The 4B5B decoder detects the receive pattern. To do this, the decoder examines
groups of 10 consecutive code bits (two 5B words) from the descrambler. Between
packets, the receiver detects the idle pattern
(5B /I/ symbols). When in the idle state, the device deasserts the CRS and RX_DV
pins.
If the receiver is in the idle state and 10 consecutive code bits from the receiver
consist of the /J/K/ symbols, the start of packet is detected, data reception begins,
and /5/5/ symbols are substituted in place of the /J/K/ symbols.
If the receiver is in the idle state and 10 consecutive code bits from the receiver are
a pattern that is neither /I/I/ nor /J/K/ symbols, but contain at least two noncontiguous
zeros, activity is detected but the start of packet is considered to be faulty and a
False Carrier Indication (also referred to as bad SSD) is signaled to the controller
interface.
When False Carrier is detected, CRS is asserted, RX_ER is asserted, RX_DV
remains deasserted, the RXD[3:0] output state is 0b1110 while RX_ER is asserted,
and the Start of Stream Error bit (SSD) is set in the MI serial port Status Output
register. Once a False Carrier Event is detected, the idle pattern (two /I/I/ symbols)
must be detected before any new SSDs can be sensed.
If the receiver is in the idle state and 10 consecutive code bits from the receiver
consist of a pattern that is neither /I/I/ nor /J/K/ symbols but does not contain at least
two noncontiguous zeros, the data is ignored and the receiver stays in the idle state.
1.3.2 10 Mbits/s
Because the idle period in 10 Mbits/s mode is defined to be when there is no valid
data on the TP inputs, the start of packet for 10 Mbits/s mode is detected when the
TP squelch circuit detects valid data. When the start of packet is detected, CRS is
asserted as described in Section 1.2.2, “Controller Interface,” page 1-16. See Section
1.2.8.4, “Squelch (10 Mbits/s),” page 1-29 for details on the squelch algorithm.
SMSC DS – LAN83C183
38
Rev. 12/14/2000