LAN83C183 Datasheet, PDF (100/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

5.3.5 Link Pulse Timing Characteristics
Table 5.12 shows the Link Pulse AC timing parameters. See Figure 5.15 and Figure
5.16 for the Link Pulse timing diagrams.
Table 5.12 Link Pulse Timing
Limit
Sym
Parameter
Min
Typ
t61
NLP Transmit Link Pulse See Figure 1.7
Width
t62
NLP Transmit Link Pulse 8
Period
t63
NLP Receive Link Pulse
50
Width Required For
Detection
t64
NLP Receive Link Pulse
6
Minimum Period Required
For Detection
t65
NLP Receive Link Pulse
50
Maximum Period Required
For Detection
t66
NLP Receive Link Pulses 3
3
Required To Exit Link Fail
State
t67
FLP Transmit Link Pulse
100
Width
t68
FLP Transmit Clock Pulse To 55.5 62.5
Data Pulse Period
t69
FLP Transmit Clock Pulse To 111
125
Clock Pulse Period
t70
FLP Transmit Link Pulse
8
Burst Period
t71
FLP Receive Link Pulse
50
Width Required For
Detection
t72
FLP Receive Link Pulse
5
Minimum Period Required
For Clock Pulse Detection
t73
FLP Receive Link Pulse
165
Maximum Period Required
For Clock Pulse Detection
t74
FLP Receive Link Pulse
15
Minimum Period Required
For Data Pulse Detection
t75
FLP Receive Link Pulse
78
Maximum Period Required
For Data Pulse Detection
Max Unit
ns
24
ms
ns
Condition
7
ms
link_test_min
150
ms
link_test_max
3
Link lc_max
Pulses
150
ns
69.5
µs
interval_timer
139
µs
22
ms
transmit_link_burst_timer
ns
25
µs
flp_test_min_timer
185
µs
flp_test_max_timer
47
µs
100
µs
data_detect_min_
timer
data_detect_max_
timer
SMSC DS – LAN83C183
100
Rev. 12/14/2000