LAN83C183 Datasheet, PDF (31/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

If the device is to be connected to a 5V external fiber optic transceiver, SD_THR must
be tied to VDD − 1.3V, which can be accomplished with an external resistor divider.
Refer to the ?Application Note? for more details on connections to external fiber optic
transceivers.
1.2.9.3 FX DISABLE
The FX interface is disabled if the SD/FXDISn pin is connected to GND; otherwise,
the FX interface is enabled. Disabling the FX interface automatically enables the TP
interface. Conversely, enabling the TP interface disables the FX interface.
1.2.10 Clock and Data Recovery
This section describes clock and data recovery methods implemented in the device
for both the 100 Mbits/s and 10 Mbits/s modes.
1.2.10.1 100 MBITS/S CLOCK AND DATA RECOVERY
Clock recovery is accomplished with a phase-locked-loop (PLL). If valid data is not
present on the receive inputs, the PLL is locked to the
25-MHz TX_CLK signal. When the squelch circuit detects valid data on the receive
TP input, and if the device is in the Link Pass state, the PLL input is switched to the
incoming data on the receive inputs. The PLL then locks on to the transitions in the
incoming signal to recover the clock. The recovered data clock is then used to
generate the 25 MHz nibble clock, RX_CLK, which clocks data into the controller
interface section.
The recovered clock extracted by the PLL latches in data from the TP receiver to
perform data recovery. The data is then converted from a single bit stream into nibble
wide data words according to the format shown in Figure 1.3
1.2.10.2 10 MBITS/S CLOCK AND DATA RECOVERY
The clock recovery process for 10 Mbits/s mode is identical to the 100 Mbits/s mode
except:
• The recovered clock frequency is a 2.5 MHz nibble clock
• The PLL is switched from TX_CLK to the TP input when the squelch indicates
valid data
• The PLL takes up to 12 transitions (bit times) to lock onto the preamble, so some
of the preamble data symbols are lost. However, the clock recovery block
recovers enough preamble symbols to pass at least six nibbles of preamble to
the receive controller interface as shown in Figure 1.3.
The data recovery process for 10 Mbits/s mode is identical to that of the
100 Mbits/s mode. As mentioned in the Manchester Decoder section, the data
recovery process inherently performs decoding of Manchester encoded data from the
TP inputs.
1.2.11 Link Integrity and AutoNegotiation
The device can be configured to implement either the standard link integrity
algorithms or the AutoNegotiation algorithm.
The standard link integrity algorithms are used solely to establish a link to and from
a remote device. The AutoNegotiation algorithm is used to establish a link to and
from a remote device and automatically configure the device for 10 or 100 Mbits/s
and Half or Full Duplex operation. The different standard link integrity algorithms for
10 and 100 Mbits/s modes are described in following subsections.
SMSC DS – LAN83C183
31
Rev. 12/14/2000