LAN83C183 Datasheet, PDF (79/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

4.6 INTERRUPTS
The device has hardware and software interrupt capability. Certain output status bits
(also referred to as interrupt bits) in the serial port trigger interrupts.
The R/LT interrupt bits (bits [14:6]) in the Channel Status Output Register cause an
interrupt when they transition provided they are not masked with the mask bits in the
Interrupt Mask register. These interrupt bits stay latched until read. When all interrupt
bits are read, the interrupt indication is removed and the interrupt bits that caused
the interrupt are updated to their current value.
Setting the appropriate mask register bits in the Interrupt Mask Register individually
can mask and remove an interrupt bit as a source of interrupt.
Interrupt indication is done in three ways:
• MDINTn pin: The MDINTn pin is an active-LOW interrupt output indication.
• INT bit: The INT bit in the Status Output Register, when set, indicates that one
or more interrupt bits have changed since the register was last read.
• Interrupt pulse on MDIO: When the Interrupt Scheme Select bit (INT_MDIO) is
set in the Configuration 2 register, an interrupt is indicated with a low-going pulse
on MDIO when MDC is high and the serial port is in the idle state, as shown in
the timing diagram in Figure 4.3. After the interrupt pulse, MDIO goes back to
the high-impedance state. If the interrupt occurs while the serial port is being
accessed, the MDIO interrupt pulse is delayed until one clock bit after the serial
port access cycle has ended, as shown in Figure 4.3
Figure 4.3 MDIO Interrupt Pulse
INTERNAL
INTERRUPT
MDC
MDIO
INTERNAL
INTERRUPT
MDC
MDIO HI-Z
Pulled High Externally
MDIO
B1
B0
Interrupt
Pulse
MDIO HI-Z
Pulled High Externally
Last Two Bits
Interrupt
of Read Cycle
Pulse
MDIO HI-Z
Pulled High Externally
MDIO HI-Z
Pulled High Externally
SMSC DS – LAN83C183
79
Rev. 12/14/2000