LAN83C183 Datasheet, PDF (85/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

Table 5.3 Twisted Pair Characteristics (Transmit (Cont.) )
Sym
TODC
TOJ
TOO
TOVT
TSOI
TLPT
TOIV
TOIA
TOIR
TORA
TOR
TOC
Limit
Parameter
Min
Typ
Max Unit
Conditions
TP Differential Output
Duty Cycle Distortion
± 0.25
nS 100 Mbits/s, output data = 0101...
NRZ pattern unscrambled, measure
at 50% Points
TP Differential Output
Jitter
± 1.4
nS 100 Mbits/s, output data = scrambled
/H/
TP Differential Output
Overshoot
5.0
% 100 Mbits/s
TP Differential Output
Voltage Template
See Figure 1.4
10 Mbits/s
TP Differential Output
SOI Voltage Template
See Figure 1.8
10 Mbits/s
TP Differential Output
Link Pulse Voltage
Template
TP Differential Output
Idle Voltage
See Figure 1.6
10 Mbits/s, NLP and FLP
± 50
mV 10 Mbits/s. Measured on secondary
side of transformer in ?Apnote?.
TP Output Current
38
40
42 mA pk 100 Mbits/s, UTP with TLVL[3:0] =
0b1000
31.06 32.66 34.26 mA pk 100 Mbits/s, STP with TLVL[3:0] =
0b1000
88
100
112 mA pk 10 Mbits/s, UTP with TLVL[3:0] =
0b1000
71.86 81.64 91.44 mA pk 10 Mbits/s, STP with TLVL[3:0] =
0b1000
TP Output Current
0.80
Adjustment Range
1.2
VDD = 3.3 V, adjustable with REXT,
relative to TOIA with REXT = 10K
0.86
1.16
VDD = 3.3 V, Adjustable with
TLVL[3:0] See ?Application Note?,
relative to value at TLVL[3:0] =
0b1000
TP Output Current TLVL
Step Accuracy
± 50
% Relative to ideal values in Figure 1.6.
Table 1.6 values relative to output
with TLVL[3:0] = 0b1000.
TP Output Resistance
10 K
Ohm
TP Output Capacitance
15
pF
SMSC DS – LAN83C183
85
Rev. 12/14/2000