LAN83C183 Datasheet, PDF (57/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

3.3 REGISTERS
This section contains a description of each of the bits in each register.
3.3.1 Control Register (Register 0)
The default value for this register is 0x3000.
15
RST
7
COLTST
14
LPBK
6
13
SPEED
12
ANEG_EN
11
PDN
10
9
MII_DIS ANEG_RST
8
DPLX
0
Reserved
RST
Reset
RST Bit Meaning
R/WSC 15
1
Reset. The bit is bit self-clearing in less than or
equal to 200 µs after reset finishes.
0
Normal (Default)
LPBK
Loopback Enable
LPBK Bit Meaning
1
Loopback mode enabled
0
Normal (Default)
R/W 14
SPEED Speed Select
SPEED Bit¹ Meaning
R/W 13
1
100 Mbit/s (100BASE-TX) (default)
0
10 Mbit/s (10BASE-T)
1. The SPEED bit is effective only when AutoNegotiation is off,
and the bit can be overridden with the assertion of the
SPEED pin.
ANEG_EN AutoNegotiation Enable
ANEG_EN
Bit¹
Meaning
R/W 12
1
1 = AutoNegotiation enabled (default)
0
0 = Disabled
1. The ANEG_EN pin can be overridden with the
assertion of the ANEG pin.
PDN
Power Down Enable
PDN Bit Meaning
1
Power down
0
Normal (default)
R/W 11
MII_DIS MII Interface Disable
MII_DIS¹ Bit
0
MII interface disable
1
Normal (default)
1. If MDA[3:0]n is not read as 0b1111 at reset
time, the MII_DIS default value is changed
to 0.
R/W 10
SMSC DS – LAN83C183
57
Rev. 12/14/2000