LAN83C183 Datasheet, PDF (90/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

5.3.1 25 MHz Input/Output Clock Timing Characteristics
Table 5.8 25 MHz Input/Output Clock¹
Limit
Sym
Parameter
Min Typ Max Unit
Conditions
t1
OSCIN Period
39.996 40 40.004 ns Clock applied to OSCIN
t2
OSCIN High Time
16
ns Clock applied to OSCIN
t3
OSCIN Low Time
16
ns Clock applied to OSCIN
t4
OSCIN to TX_CLK Delay
10
ns 100 Mbits/s
1. Refer to Figure 5.1 for Timing Diagram
20
ns 10 Mbits/s
Figure 5.1 25 MHz Output Timing
OSCIN
TX_CLK
(100 Mbits/s)
TX_CLK
(10 Mbits/s)
t₁
t₄
t₄
t₂
t₃
t₄
SMSC DS – LAN83C183
90
Rev. 12/14/2000