LAN83C183 Datasheet, PDF (11/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

Chapter 1
LAN83C183
Functional Description
This chapter is a functional description of the PHY device with the following sections:
• Section 1.1, “Overview”
• Section 1.2, “Block Diagram Description”
• Section 1.3, “Start of Packet”
• Section 1.4, “End of Packet”
• Section 1.5, “Full/Half Duplex Mode”
• Section 1.6, “Repeater Mode”
• Section 1.7, “10/100 Mbits/s Selection”
• Section 1.8, “Jabber”
• Section 1.9, “Automatic Jam”
• Section 1.10, “Reset”
• Section 1.11, “Powerdown”
• Section 1.12, “Receive Polarity Correction”
1.1 OVERVIEW
This section gives a brief overview of the device functional operation. The
LAN83C183 is a complete 10/100 Mbits/s Ethernet Media Interface IC. A block
diagram is shown in Figure 1.1.
1.1.1 Channel Operation
The PHY operates in the 100BASE-TX or 100BASE-FX modes at 100 Mbits/s, or in
the 10BASE-T mode at 10 Mbits/s. The 100 Mbits/s modes and the 10 Mbits/s mode
differ in data rate, signaling protocol, and allowed wiring as follows:
• 100BASE-TX mode uses two pairs of category 5 or better UTP or STP twisted-
pair cable with 4B5B encoded, scrambled, and MLT3 coded 62.5-MHz ternary
data to achieve a throughput of 100 Mbits/s.
• The 100BASE-FX mode uses two fiber cables with 4B5B encoded, 125-MHz
binary data to achieve a throughput of 100 Mbits/s.
• 10 Mbits/s mode uses two pairs of category 3 or better UTP or STP twisted-pair
cable with Manchester encoded 10-MHz binary data to achieve a 10 Mbits/s
throughput
The data symbol format on the twisted-pair cable for the 100 and 10 Mbits/s modes
is defined in IEEE 802.3 specifications and shown in Figure 1.2.
1.1.2 Data Paths
In each device, there is a transmit data path and a receive data path associated with
each PHY channel. The transmit data path is from the Controller Interface to the
twisted-pair transmitter. The receive data path is from the twisted-pair receiver to the
Controller Interface.
SMSC DS – LAN83C183
11
Rev. 12/14/2000