LAN83C183 Datasheet, PDF (41/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

1.5 FULL/HALF DUPLEX MODE
Half-Duplex mode is the CSMA/CD operation defined in IEEE 802.3. It allows
transmission or reception, but not both at the same time. Full-Duplex operation is a
mode that allows simultaneous transmission and reception. Full duplex in the 10
Mbits/s mode is identical to operation in the 100 Mbits/s mode.
The device can be forced into either the Full- or Half-Duplex mode, or the device can
use AutoNegotiation to autoselect Full/Half-Duplex operation. When the device is
placed in Full-Duplex mode:
• The collision function is disabled, and
• TX_EN to CRS loopback is disabled
1.5.1 Forcing Full/Half Duplex Operation
To independently force a channel into either the Full- or Half-Duplex mode, set the
Duplex Mode Select (DPLX) bit in the MI serial port Control register, or assert the
DPLX pin, assuming that AutoNegotiation is not enabled with the ANEG_EN bit in
the MI serial port Control register.
The device automatically configures itself for Full- or Half-Duplex mode. To do this,
the device uses the AutoNegotiation algorithm to advertise and detect Full and Half
Duplex capabilities to and from a remote device. To enable AutoNegotiation, set the
AutoNegotiation Enable (ANEG_EN) bit in the MI serial port Control register or assert
the ANEG pin.
To select the advertised Full/Half Duplex capability, appropriately set the bits in the
MI serial port AutoNegotiation Advertisement register. AutoNegotiation functionality is
described in more detail in Section 1.2.11, “Link Integrity and AutoNegotiation”.
1.5.2 Full/Half Duplex Indication
Full Duplex detection can be monitored through the Duplex Detect bit (DPLX_DET)
in the MI serial port Status Output register.
The device can also be programmed such that the Full-Duplex indication appears on
the PLED1n pin. To do this, appropriately set the Programmable LED Output Select
bits in the MI serial port Configuration 2 register as described in Table 1.9. When the
PLED1n pin is programmed to be a Full-Duplex detect output, it is asserted LOW
when the device is configured for Full Duplex operation. The PLED1 output has both
pullup and pulldown driver transistors and a weak pullup resistor, so it can drive an
LED from either V_DD or GND and can also drive a digital input.
1.5.3 Loopback
1.5.3.1 INTERNAL CRS LOOPBACK
TX_EN is internally looped back onto CRS during every transmit packet. This internal
CRS loopback is disabled during collision, in Full-Duplex mode, in the Link Fail State,
and when the Transmit Disable bit (XMT_DIS) is set in the MI serial port
Configuration 1 register. In 10 Mbits/s mode, internal CRS loopback is also disabled
when jabber is detected.
1.5.3.2 DIAGNOSTIC LOOPBACK
Setting the loopback bit (LPBK) in the MI serial port Control register selects the
diagnostic loopback mode. When diagnostic loopback is enabled, the TXD[3:0] data
is looped back onto RXD[3:0], TX_EN is looped back onto CRS, RX_DV operates
normally, the TP receive and transmit paths are disabled, the transmit link pulses are
SMSC DS – LAN83C183
41
Rev. 12/14/2000