LAN83C183 Datasheet, PDF (27/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

1.2.7.4 TRANSMIT RISE AND FALL TIME ADJUST
The transmit output rise and fall time can be adjusted with the two Transmit Rise/Fall
time adjust bits (TRF[1:0]) in the MI serial port Configuration 1 register. The
adjustment range is −0.25 ns to +0.5 ns in 0.25 ns steps.
1.2.7.5 STP (150 OHM) CABLE MODE
The transmitter can be configured to drive 150 Ω shielded twisted-pair cable. To
enable this configuration, set the Cable Type Select bit (CABLE) in the MI serial port
Configuration 1 register. When STP mode is enabled, the output current is
automatically adjusted to comply with IEEE 802.3 levels.
1.2.7.6 TRANSMIT ACTIVITY INDICATION
Appropriately setting the programmable LED Output Select bits in the MI serial port
LED Configuration 2 register programs transmit activity to appear on some of the
PLED[5:0]n pins. When one or more of the PLED[5:0]n pins is programmed to be an
activity or transmit activity detect output, that pin is asserted LOW for 100 ms every
time a transmit packet occurs. The PLED[5:0]n outputs are open-drain with resistor
pullup and can drive an LED from V_DD or can drive other digital inputs. See Section
1.2.14, “LED Drivers,” page 1-36 for more detailed information on the LED outputs.
1.2.7.7 TRANSMIT DISABLE
Setting the Transmit Disable bit (XMT_DIS) in the MI serial port Configuration 1
register disables the TP transmitter. When the bit is set, the TP transmitter is forced
into the idle state, no data is transmitted, no link pulses are transmitted, and internal
loopback is disabled.
1.2.7.8 TRANSMIT POWERDOWN
Setting the Transmit Powerdown bit (XMT_PDN) in the MI serial port Configuration
1 register powers down the TP transmitter. When the bit is set, the TP transmitter is
powered down, the TP transmit outputs are high impedance, and the rest of the
LAN83C183 operates normally.
1.2.8 Twisted-Pair Receivers
The device is capable of operating at either 10- or 100-Mbits/s. This section
describes the twisted-pair receivers and squelch operation for both modes of
operation.
1.2.8.1 100 MBITS/S TP RECEIVER
The TP receiver detects input signals from the twisted-pair input and converts them
to a digital data bit stream ready for clock and data recovery. The receiver can
reliably detect 100BASE-TX compliant transmitter data that has been passed through
0 to 100 meters of
100 Ω category 5 UTP or 150-ohm STP cable.
The 100 Mbits/s receiver consists of an adaptive equalizer, baseline wander
correction circuit, comparators, and an MLT3 decoder. The TP inputs first go to an
adaptive equalizer. The adaptive equalizer compensates for the low-pass
characteristics of the cable, and can adapt and compensate for 0 to 100 meters of
category 5, 100-ohm or 150-ohm STP cable. The baseline wander correction circuit
restores the DC component of the input waveform that the external transformers
have removed. The comparators convert the equalized signal back to digital levels
and qualify the data with the squelch circuit. The MLT3 decoder takes the three-level
SMSC DS – LAN83C183
27
Rev. 12/14/2000