LAN83C183 Datasheet, PDF (76/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

bit in the MI serial port Configuration 2 Register enables the multiple register access
feature.
When the PHYAD[4:0] bits in the MI frame match MDA[4:0]n pins on the device and
the REGAD[4:0] bits are set to 0b11111 during the first 16 clock cycles, all 11
registers are accessed on the 176 rising edges of MDC (11 registers x 16 bits per
register) that occur after the first 16 MDC clock cycles of the MI serial port access
cycle. There is no actual register residing at 0b1111, but this condition triggers the
access of multiple registers.
The registers (0, 1, 2, 3, 4, 5, 16, 17, 18, 19, and 20) are accessed in numerical
order from 0 to 20. After all 192 MDC clocks (16 + 176) have been completed:
• All the registers have been read or written
• The serial shift process is halted
• Data is latched into the device
• MDIO goes into a high-impedance state.
Another serial shift cycle cannot be initiated until the idle condition (at least 32
continuous ones) is detected.
SMSC DS – LAN83C183
76
Rev. 12/14/2000