LAN83C183 Datasheet, PDF (91/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

5.3.2 Transmit Timing Characteristics
Table 5.9 shows the Transmit AC timing parameters. See Figure 5.2 and Figure 5.3
for the 100 Mbits/s and 10 Mbits/s transmit timing diagrams.
Table 5.9 Transmit Timing
Sym
t11
t12
t13
t14
t15
t16
t17
Parameter
TX_CLK Period
TX_CLK Low Time
TX_CLK High Time
TX_CLK Rise/Fall Time
TX_EN Setup Time
TX_EN Hold Time
CRS During Transmit Assert Time
Min
39.996
399.96
16
160
16
160
15
0
t18
CRS During Transmit Deassert
Time
t19
TXD Setup Time
15
t20
TXD Hold Time
0
t21
TX_ER Setup Time
15
t22
TX_ER Hold Time
0
t23
Transmit Propagation Delay
60
t24
Transmit Output Jitter
t25
Transmit SOI Pulse Width To 0.3 V 250
t26
Transmit SOI Pulse Width to 40 mV
t27
PLEDn Delay Time
t28
PLEDn Pulse Width
80
Limit
Typ
40
400
20
200
20
200
Max
40.004
400.04
24
240
24
240
10
40
400
160
900
140
140
600
± 0.7
± 5.5
4500
25
105
Unit
Conditions
ns 100 Mbits/s
ns 10 Mbits/s
ns 100 Mbits/s
ns 10 Mbits/s
ns 100 Mbits/s
ns 10 Mbits/s
ns
ns
Note¹
ns
ns 100 Mbits/s
ns 10 Mbits/s
ns 100 Mbits/s
ns 10 Mbits/s
ns Note 1
ns
ns Note 1
ns
ns 100 Mbits/s, MII
ns 100 Mbits/s, FBI
ns 10 Mbits/s
ns pk-pk 100 Mbits/s
ns pk-pk 10 Mbits/s
ns 10 Mbits/s
ns 10 Mbits/s
ms PLEDn programmed
for activity
ms PLEDn programmed
for activity
1. Setup time measured with 5 pF loading on TXC. Additional leading will create a delay on TXC rise time, which
requires increased setup times.
SMSC DS – LAN83C183
91
Rev. 12/14/2000