LAN83C183 Datasheet, PDF (29/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

The device stays in the unsquelch state until loss of data is detected. Loss of data
is detected if no alternating polarity unsquelch transitions are detected during any 10
µs interval. When a loss of data is detected, the receive squelch is turned on again.
1.2.8.4 SQUELCH (10 MBITS/S)
The TP squelch algorithm for 10 Mbits/s mode is identical to the
100 Mbits/s mode, except:
• The 10 Mbits/s TP squelch algorithm is not used for link integrity, but to sense
the beginning of a packet
• The receiver goes into the unsquelch state if the input voltage exceeds the
squelch levels for three bit times with alternating polarity within a 50 to 250 ns
interval
• The receiver goes into the squelch state when SOI is detected
• Unsquelch detection has no effect on link integrity (link pulses are used in 10
Mbits/s mode for that purpose)
• Start of packet is determined when the receiver goes into the unsquelch state
and CRS is asserted
• The receiver meets the squelch requirements defined in IEEE 802.3 Clause 14.
1.2.8.5 EQUALIZER DISABLE
Setting the Equalizer Disable bit (EQLZR) in the MI serial port Configuration 1
register disables the adaptive equalizer. When disabled, the equalizer is forced into
the response it would normally have if zero cable length was detected.
1.2.8.6 RECEIVE LEVEL ADJUST
Setting the Receive Level Adjust bit (RLV0) in the MI serial port Configuration 1
register lowers the receiver squelch and unsquelch levels by 4.5 dB. Setting this bit
may allow the device to support longer cable lengths.
1.2.8.7 RECEIVE ACTIVITY INDICATION
Appropriately setting the programmable LED output select bits in the MI serial port
LED Configuration 2 register programs receive activity to appear on some of the
PLED[5:0]n pins. When one or more of the PLED[5:0]n pins is programmed to be a
receive activity or activity detect output, that pin is asserted LOW for 100 ms every
time a receive packet occurs. The PLED[5:0]n outputs are open-drain with resistor
pullup and can drive an LED from V_DD or can drive another digital input. See Section
1.2.14, “LED Drivers,” page 1-36 for more detailed information on the LED outputs.
1.2.9 FX Transmitter and Receiver
The FX transmitter and receiver implement the 100BASE-FX function defined in IEEE
802.3. 100BASE-FX is intended for transmission and reception of data over fiber and
is specified to operate at 100 Mbits/s. Thus, the FX transmitter and receiver in the
device only operate when the device is placed in 100 Mbits/s mode.
1.2.9.1 TRANSMITTER
The FX transmitter converts data from the 4B5B encoder into binary NRZI data and
outputs the data onto the FXO+/- pins. The output driver is a differential current
source that is able to drive a 100 Ω load to ECL levels. The FXO+/- pins can directly
drive an external fiber optic transceiver. The FX transmitter meets all the
requirements defined in IEEE 802.3.
SMSC DS – LAN83C183
29
Rev. 12/14/2000