LAN83C183 Datasheet, PDF (58/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

ANEG_RSTAutoNegotiation Reset
R/WSC 9
ANEG_RST Bit
1
Restart AutoNegotiation process. The bit is
self-clearing after reset is finished
0
Normal (default)
DPLX
Duplex Mode Select
DPLX Bit¹
1
Full-duplex
0
Half-duplex (default)
1. This bit is effective only when AutoNegotia-
tion is off, and the bit can be overridden with
the assertion of the DPLX pin.
R/W 8
COLTST Collision Test Enable
COLTST Bit
1
Collision test enabled
0
Normal (default)
R/W 7
R
Reserved
R [6:0]
These bits are reserved and must be remain at the default value of
0x00 for proper device operation.
3.3.2 Status Register (Register 1)
The default value of this register is 0x7809.
15
CAP_T4
14
13
CAP_TXF CAP_TXH
12
CAP_TF
11
CAP_TH
7
6
5
4
3
Reserved CAP_SUPR ANEG_ACK REM_FLT CAP_ANEG
10
2
LINK
CAP_T4 100BASE-T4 Capable
R 15
CAP_T4
Bit Meaning
1 Capable of 100BASE-T4 operation
0 Not capable of 100BASE-T4 Operation (default)
CAP_TXF 100BASE-TX Full Duplex Capable R 14
CAP_TXF
Bit Meaning
1 Capable of 100BASE-TX Full-Duplex (default)
0 Not capable of 100BASE-TX Full-Duplex
CAP_TXH 100BASE-TX Half Duplex Capable R 13
CAP_TXH
Bit Meaning
1 Capable of 100BASE-TX Half-Duplex (default)
0 Not capable of 100BASE-TX Half-Duplex
Reserved
1
JAB
8
0
EXREG
SMSC DS – LAN83C183
58
Rev. 12/14/2000