LAN83C183 Datasheet, PDF (40/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

Figure 1.8 SOI Output Voltage Template - 10 Mbits/s
3.1 V
0 BT
4.5 BT
0.5 V/ns
585 mV
0.25 BT
2.25 BT
6.0 BT
585 mV sin (2 ∗ π ∗ (t/1 BT))
0 ≤ t ≤ 0.25 BT and
225 ≤ t ≤ 2.5 BT
+ 50 mV
− 50 mV
45.0 BT
− 3.1 V
2.5 BT 4.5 BT
The TP receiver senses missing data transitions in order to detect the receive SOI
pulse. Once the SOI pulse is detected, data reception is ended and the CRS and
RX_DV pins are deasserted.
SMSC DS – LAN83C183
40
Rev. 12/14/2000