LAN83C183 Datasheet, PDF (55/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

3.2 MI SERIAL PORT REGISTER SUMMARY
The following tables summarize the device registers accessible through the MI serial
port.
Control Register (register 0) –
15
RST
7
COLTST
14
LPBK
6
13
SPEED
12
ANEG_EN
11
PDN
10
9
MII_DIS ANEG_RST
8
DPLX
0
Reserved
Status Register (register 1) –
15
14
13
12
11
10
CAP_T4 CAP_TXF CAP_TXH CAP_TF CAP_TH
7
6
5
4
3
Reserved CAP_SUPR ANEG_ACK REM_FLT CAP_ANEG
2
LINK
PHY ID #1 Register (register 2) –
15
OUI3
14
OUI4
13
OUI5
12
OUI6
11
OUI7
10
OUI8
7
OUI11
6
OUI12
5
OUI13
4
OUI14
3
OUI15
2
OUI16
PHY ID #2 Register (register 3) –
15
OUI19
14
OUI20
13
OUI21
12
OUI22
11
OUI23
10
OUI24
7
PART3
6
PART2
5
PART1
4
PART0
3
REV3
2
REV2
AutoNegotiation Advertisement Register (register 4) –
15
14
13
NP
ACK
RF
12
10
Reserved
7
6
5
4
TX_HDX 10_FDX 10_HDX
Reserved
AutoNegotiation Remote End Capability Register (register 5) –
15
14
13
NP
ACK
RF
12
10
Reserved
7
6
5
4
TX_HDX 10_FDX 10_HDX
Reserved
Reserved
1
JAB
8
0
EXREG
9
OUI9
1
OUI17
8
OUI10
0
OUI18
9
PART5
1
REV1
8
PART4
0
REV0
9
8
T4
TX_FDX
1
0
CSMA
9
8
T4
TX_FDX
1
0
CSMA
SMSC DS – LAN83C183
55
Rev. 12/14/2000