LAN83C183 Datasheet, PDF (48/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

TX_EN
Transmit Enable Input
I
TX_EN must be asserted HIGH to indicate that data on TXD and
TX_ER is valid. TX_ER is clocked in on the rising edge of TX_CLK
and OSCIN.
TX_ER/TXD4
Transmit Error Input/Fifth Transmit Data Input
I
The TXER pin, when asserted, causes a special pattern to be trans-
mitted on the twisted-pair outputs in place of normal data, and it is
clocked in on the rising edge of TX_CLK when TX_EN is asserted.
If the device is placed in the Bypass 4B5B Encoder mode (the
BYP_ENC bit is set in the MI serial port Configuration 1 register), this
pin is reconfigured to be the fifth TXD transmit data input, TXD4.
2.3 MANAGEMENT INTERFACE
MDC
MI Clock
I
The MDC clock shifts serial data for the internal registers into and out
of the MDIO pin on its rising edge.
MDINTn/MDA4n
Management Interface Interrupt Output/
Management Interface Address Input Pullup O.D. I/O
This pin is an interrupt output and is asserted LOW whenever there
is a change in certain MI serial port register bits. The pin is deas-
serted after all changed bits have been read out.
During powerup or reset, this pin is high impedance and the state of
the pin is latched in as the physical device address MDA4 for the MI
serial port.
MDIO
MI Data
I/O
This bidirectional pin contains serial data for the internal registers.
The data on this pin is clocked in and out of the device on the rising
edge of MDC.
2.4 MISCELLANEOUS SIGNALS
ANEG
AutoNegotiation Input
I
This pin control AutoNegotiation operation.
ANEG Pin
HIGH
LOW
Meaning
AutoNegotiation is on.
AutoNegotiation Enable is controlled
from the ANEG_EN bit, 10/100 Mbits/s
operation is controlled from the
SPEED bit, and Half/Full Duplex
operation is controlled from the DPLX
bit.
AutoNegotiation is off.
10/100 Mbits/s operation is controlled
from the SPEED pin and Half/Full
Duplex operation is controlled from the
DPLX pin.
SMSC DS – LAN83C183
48
Rev. 12/14/2000