LAN83C183 Datasheet, PDF (20/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

bypass the 4B5B encoder/decoder, set the Bypass Encoder bit (BYP_ENC) in the MI
serial port Configuration 1 register.
When the FBI is enabled, it may also be desirable to bypass the
scrambler/descrambler and disable the internal CRS loopback function. To bypass
the scrambler/descrambler, set the Bypass Scrambler bit (BYP_SCR) in the MI serial
port Configuration 1 register. To disable the internal CRS loopback, set the TX_EN
to CRS loopback disable bit (TXEN_CRS) in the MI serial port Configuration 1
register.
MII Selection – To disable the MII (and FBI) inputs and outputs, set the MII_DIS bit in
the MI serial port Control register. When the MII is disabled, the MII and FBI inputs
are ignored, and the MII, FBI, and TPI outputs are placed in a high-impedance state.
The MII pins affected are:
• RX_CLK
• RXD[3:0]
• RX_DV
• RX_ER
• COL
If the MI address lines, MDA[4:0]n, are pulled HIGH during reset or powerup, the
LAN83C183 powers up and resets with the MII and FBI disabled. Otherwise, the
LAN83C183 powers up and resets with the MII and FBI enabled.
In addition, when the R/J_CFG bit in the MI serial port Configuration 1 register is
LOW, the RX_EN/JAMn pin is configured for RX_EN operation. If the RX_EN pin is
LOW in this situation, the MII controller interface outputs are placed in the high-
impedance state.
1.2.3 Encoder
This section describes the 4B5B encoder, which is used in 100 Mbits/s operation. It
also describes the Manchester Encoder, used in 10BASE-T operation.
1.2.3.1 4B5B ENCODER (100 MBITS/S)
100BASE-TX operation requires that the data be 4B5B encoded. The 4B5B Encoder
block shown in Figure 1.1 converts the four-bit data nibbles into five-bit data words.
The mapping of the 4B nibbles to 5B codewords is specified in IEEE 802.3 and is
shown in Table 1.4.
SMSC DS – LAN83C183
20
Rev. 12/14/2000