LAN83C183 Datasheet, PDF (47/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

2.2 CONTROLLER INTERFACE SIGNALS (MII)
CRS
Carrier Sense Output
O
The CRS output is asserted HIGH when valid data is detected on the
receive TP inputs. CRS is clocked out on the falling edge of RX_CLK.
OSCIN
Clock Oscillator Input
I
There must be either a 25 MHz crystal between this pin and GND or
a 25 MHz clock applied to this pin. TX_CLK output is generated from
this input.
RX_CLK
Receive Clock Output
O
Receive data on RXD, RX_DV, and RX_ER is clocked out to an
external controller on the falling edge of RX_CLK.
RXD[3:0]
Receive Data Output
O
RXD[3:0] contain receive nibble data from the TP input, and they are
clocked out on the falling edge of RX_CLK.
RX_DV
Receive Data Valid Output
O
RX_DV is asserted HIGH when valid decoded data is present on the
RXD outputs. RX_DV is clocked out on the falling edge of RX_CLK.
RX_EN/JAMn Receive Enable Input
I
The function of this pin is configured through the R/J Configuration
Select bit (R/J_CFG) in the MI serial port Configuration 1 register.
When R/J_CFG is set, the pin is configured as JAMn; when it is
cleared, the pin functions as RX_EN
RX_EN function: when RX_EN is HIGH, all of the receive outputs
(RX_CLK, RXD[3:0], RX_DV, RX_ER, COL) are enabled. When
RX_EN is LOW, the outputs are in a
high-impedance state.
JAMn function: when JAMn is HIGH, a JAM packet is transmitted
when receive activity is detected. When JAMn is LOW, no JAM
packet is transmitted.
RXER/RXD4
Receive Error Output/Fifth Receive Data Output O
The RXER/RXD4 output is asserted HIGH when a coding error or
other specified errors are detected on the receive twisted-pair inputs.
The signal is clocked out on the falling edge of RX_CLK.
If the device is placed in the Bypass 4B5B Decoder mode (the
BYP_ENC bit is set in the MI serial port Configuration 1 register), this
pin is reconfigured to be the fifth RXD receive data output, RXD4.
TX_CLK
Transmit Clock Output
O
Transmit data from the controller on TXD, TX_EN, and TX_ER is
clocked in on the rising edge of TX_CLK and OSCIN.
TXD[3:0]
Transmit Data Input
I
TXD[3:0] contain input nibble data to be transmitted on the TP out-
puts, and they are clocked in on the rising edge of TX_CLK and
OSCIN when TX_EN is asserted.
SMSC DS – LAN83C183
47
Rev. 12/14/2000