LAN83C183 Datasheet, PDF (75/113 Pages) SMSC Corporation – FAST ETHERNET PHYSICAL LAYER DEVICE

4.2 GENERAL OPERATION
The MI serial port is idle when at least 32 continuous ones are detected on the bi-
directional MDIO data pin and remains idle as long as continuous ones are detected.
During idle, the MDIO output driver is in the high-impedance state. When the MI
serial port is in the idle state, a 0b01 pattern on the MDIO pin initiates a serial shift
cycle. Control and address bits are clocked into MDIO on the next 14 rising edges
of MDC (the MDIO output driver is still in a high-impedance state). If the multiple
register access mode is not enabled, data is either shifted in or out on MDIO on the
next 16 rising edges of MDC, depending on whether a write or read cycle was
selected with the READ and WRITE operation bits. After the 32 MDC cycles have
been completed:
• One complete register has been read or written
• The serial shift process is halted
• Data is latched into the device
• The MDIO output driver goes into a high-impedance state.
Another serial shift cycle cannot be initiated until the idle condition is detected again
(at least 32 continuous ones). Figure 4.1 shows a timing diagram for a MI serial port
cycle.
Figure 4.1 MI Serial Port Frame Timing Diagram
WRITE Cycle
MDC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MDIO
0
10
1 P4 P3 P2 P1 P0 R4 R3 R2 R1 R0 1
0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ST OP
PHYAD
REGAD
TA
DATA
WRITE Bits
PHY clocks in data on rising edges of MDC with t_s = 10 ns minimum and t_h = 10 ns minimum
READ Cycle
MDC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MDIO
0
11
0 P4 P3 P2 P1 P0 R4 R3 R2 R1 R0 Z 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ST OP
PHYAD
REGAD
TA
DATA
WRITE Bits
PHY clocks in data on rising edges of MDC with
t_s = 10 ns minimum, and t_h = 10 ns minimum
READ Bits
PHY clocks out data on rising edges of MDC with
t_d = 20 ns maximum
Note: ST = start bits, OP = operation bits (read or write), PHAD = PHY address, REGAD = register address, TA = turnaround bits
For more detailed timing information on t_h, t_h, and t_h, see Chapter 6, “Specifications.”
4.3 MULTIPLE REGISTER ACCESS
Multiple registers can be accessed on a single MI serial port access cycle with the
multiple register access feature. Setting the Multiple Register Access Enable (MREG)
SMSC DS – LAN83C183
75
Rev. 12/14/2000