HD66781 Datasheet, PDF (99/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
RAM Address and Display Position on the Panel
The HD66781 incorporates a memory for 240RGB x 416-line display, and enables to drive QVGA-size
panel (240RGB x 320 lines). Unused display memory is available for a partial OSD area. These features
realize various ways of display with a single chip.
The HD66781 allows independent settings for the display panel and the drive position, where the RAM
area of each image is specified in relation to the display panel that is assigned to gate pins to fit into the
assembly. Accordingly, in designing a panel, it is not necessary to take the assembly position into account.
The HD66781 allows realizes various ways of display with the following settings:
1.
Specify the RAM area of a base image (BSA, BEA)
2.
Specify the RAM area of an OSD image (OSAx, OEAx)
3.
Specify the display position of the OSD image (step 2) on the panel (ODPx).
4.
Specify the gate pins for driving the panel displaying a base image (SCN, NL) and the
scan order (GS).
5.
Execute display ENABLE (BASEE, OSDE0/1/2) for each image after turning on display.
A base image is a display that is set to be a basic display on each panel. An OSD image is a picture that is
set to display on the base image. The panel-drive settings are made with gate scan starting position (SCN),
the number of raster-rows to drive (NL), and scan direction (GS). The gate scan direction can be set
differently for each panel to fit into the assembly. To change the display position horizontally, the setting
of SS bit is required during RAM write.
Table 53
Display ENABLE
Numbers of lines
(Base image 1)
BASEE
NL
Note 1) The base image is displayed from the start line of each panel.
Note 2) Make sure that base image RAM area is NL ≤ BEA – BSA.
RAM area
(BSA, BEA)
Table 54
OSD image 1
OSD image 2
OSD image 3
Display ENABLE
OSDE0
OSDE1
OSDE2
Display position
ODP0
ODP1
ODP2
RAM area
(OSA0, OEA0)
(OSA1, OEA1)
(OSA2, OEA2)
Rev.0.5, July.31.2003, page 99 of 196