HD66781 Datasheet, PDF (63/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Gate Driver/LTPS LCD Panel Interface Control 8 (R018h)
Preliminary
R/W RS
W1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
0 0 0 00
00 0
00
00
0
SDTE SDTE _SDTE
2 10
SDTE[2:0]: Specify the delay from a reference point of the source output during display operation with
DOTCLK (DM = 2’h1).
See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD
panel interface are controlled by these settings.
Table 41
SDTE[2:0] Source output delay
3’h0
1 clock
3’h1
2 clocks
3’h2
3 clocks
3’h3
4 clocks
3’h4
5 clocks
3’h5
6 clocks
3’h6
7 clocks
3’h7
Setting disabled
Note 1) The clocks in the tables are DOTCLK / division ratio for the 1H period, measured from a reference
point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is
set to 0 clock.
Rev.0.5, July.31.2003, page 63 of 196