HD66781 Datasheet, PDF (140/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
In the RGB interface mode, VYSNC, HSYNC and DOTCLK must be supplied more than to achieve the
resolution on the liquid crystal panels.
Polarities of VSYNC, HSYNC, ENABLE, DOTCLK signals
The polarities of VSYNC, HSYNC, ENABLE, DOTCLK signals are changeable by instruction settings
(DPL, EPL, HSPL, and VSPL) to conform to the system.
RGB interface timing
Timing chart of signals in 16/18-bit RGB interface mode
1 frame
Back porch period
VSYNC
Front porch period
HSYNC
DOTCLK
ENABLE
PD17-0
VSYNC
HSYNC
HLW҈ 1CLK
DOTCLK
1 clock
ENABLE
DTST ҈1CLK
1H or more
1H
PD17-0
Valid data
Note 1)VLW: VSYNC “Low” period
HLW: HSYNC “Low” period
DTST: Setup time for data transfer
Note 2) Write data in the high speed write mode (HWM = 1) in the RGB I/F mode.
Rev.0.5, July.31.2003, page 140 of 196