HD66781 Datasheet, PDF (10/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
Signals
DB1/SDO
Number of I/O
Pins
1
I/O
DB2~DB17 16
I/O
RESET* 1
I
RESETO1 2
O
RESETO2
OSC1
2
I or
OSC2
O
Connected Functions
to
MPU
MPU
MPU or
external
R-C circuit
18-bit parallel bi-directional data bus.
8-bit bus: DB17-DB10
9-bit bus: DB17-DB9
16-bit bus: DB17-DB10 and DB8-DB1
18-bit bus: DB17-DB0
Serial data output pin (SDO) in the Serial Peripheral Interface
mode to output data on the falling edge of SCL signal.
18-bit parallel bi-directional data bus.
8-bit bus: DB17-DB10
9-bit bus: DB17-DB9
16-bit bus: DB17-DB10 and DB8-DB1
18-bit bus: DB17-DB0
Reset pin. Initialize the LSI at the “Low” level.
A power-on reset required after turning on the power.
HD66783 or ^{Output the same polarity level as RESET*.}
HD667P21 ^{Control both HD66781 and HD66783 or HD66781 and}
HD667P21 by connecting to HD66783 or HD667P21.
Oscillation Connect an external resistor for R-C oscillation.
resistor
Unused
pins
IOVcc
IOVcc
-
Open
-
ENABLE 1
VSYNC 1
HSYNC 1
DOTCLK 1
PD0~PD17 18
I
MPU or
Data enable signal in the RGB interface mode.
LCDC
Low: Select (accessible)
High: Not select (inaccessible)
GND/
IOVcc
ENABLE signal inverts the polarity according to the setting of
EPL resister. Set ENABLE inactive while it is not used and its
level is fixed or the polarity is set with registers.
I
MPU or
Frame synchronizing signal.
GND/
LCDC
This signal is active low.
IOVcc
The polarity of VSYNC is inverted by setting VSPL register.
Set VSYNC inactive while it is not used and its level is fixed or
the polarity is set with registers.
I
MPU or
Line synchronizing signal.
LCDC
This signal is active low.
GND/
IOVcc
The polarity of HSYNC is inverted by setting HSPL register.
Set HSYNC inactive while it is not used and its level is fixed or
the polarity is set with registers.
I
MPU or
Dot clock signal. The timing of data input is determined at the GND/
LCDC
rising edge. This signal is active low.
IOVcc
The polarity of DOTCLK is inverted by setting DPL register.
Set DOTCLK inactive while it is not used and its level is fixed or
the polarity is set with registers.
I
MPU or
18-bit bus for RGB data.
LCDC
6-bit bus: PD17-PD12
16-bit bus: PD17-PD13 and PD11-PD1
18-bit bus: PD17-PD0
GND/
IOVcc
Rev.0.5, July.31.2003, page 10 of 196