HD66781 Datasheet, PDF (52/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
As the following table shows, an optimum interface is selected for the kind of display by the external
display interface control setting.
Write display data during moving picture display (through RGB and VSYNC interfaces) in the high-speed
write mode (HWM=1), which enables high-speed RAM access with low power consumption.
Table 31
Kind of Display
Operation mode
RAM access setting
(RM)
Display operation mode
(DM)
still picture
internal clock
operation only
system interface (RM = 0)
internal clock operation
(DM = 2’h0)
moving picture
RGB interface (1)
RGB interface (RM = 1)
RGB interface
(DM = 2’h1)
Write over still picture area
during moving picture display
RGB interface (2)
system interface (RM = 0)
RGB interface
(DM = 2’h1)
moving picture
VSYNC interface
system interface (RM = 0)
VSYNC interface
(DM = 2’h2)
Note 1) The instruction register settings are made only through a system interface.
Note 2) No switching between the RGB and VSYNC interfaces is made.
Note 3) No change in the settings of RGB interface mode (RIM) is made during the RGB interface operation.
Note 4) See “External Display Interface” for reference to the transition flows between the modes.
Note 5) Use the RGB and VSYNC interfaces in the high-speed write mode (HWM =1).
Internal clock mode: All display operations are controlled by signals generated by the internal clock in
internal clock operation mode. All inputs through the external display interface are invalid. The internal
RAM is accessible only through a system interface.
RGB interface mode (1): Display operation is controlled by the frame synchronizing clock (VSYNC), line
synchronizing signal (VSYNC), and dot clock (DOTCLK) in the RGB interface mode. These signals must
be supplied throughout the display operation in this mode.
All display data are stored in the internal RAM, transmitted through DB17-0 bits by pixel. The
combination with the window address function enables simultaneous display of both moving picture areas
and the internal RAM area. The data are transmitted only when the screen is being updated, thereby
reducing the overall data transmission to minimum.
The periods of the front (FP) and back (BP) porches and the display period (NL) are automatically
generated in the HD66782 by counting the clock of line synchronizing signal (HSYNC) in accordance to
the frame synchronizing signal (VSYNC). Transmit pixel data through DB17-0 bits in accordance with the
aforementioned setting.
RGB interface mode (2): When RGB-I/F is selected, RAM data are changeable through the system
interface. This write operation must be performed while display data are not being transmitted through the
RGB-I/F (ENABLE = High). When reverting from the system interface mode to the data transmission
through the RGB interface, make a new setting for the address set and index (R202h) after changing the
aforementioned settings.
Rev.0.5, July.31.2003, page 52 of 196