HD66781 Datasheet, PDF (147/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
Notes to the external display interface
1. While an external display interface is selected, the following functions are not available.
Table 66
Function
Partial display
Scroll function
Interlaced drive
External Display Interface
Not available
Not available
Not available
Internal Display Operation
Available
Available
Available
2. The VSYNC, HSYNC, and DOTCLK signals must be supplied through the display operation through
the RGB-I/F.
3. When making settings for gate driver/LTPS panel controlling signal in the RGB-I/F modes, the
reference clock is DOTCLK, not the internal operation clocks.
4. In the 6-bit RGB-I/F mode, the RGB (pixels) data are transmitted by three clocks.
5. In the 6-bit RGB-I/F mode, the interface signals, VSYNC, HSYNC, DOTCL, ENABLE, and PD17-0,
should be set by RGB (pixels) unit in convenience for the transmitting RGB pixels.
6. The transitions between the internal operation mode and external display interface should be made
according to the mode switching sequence below.
7. In the RGB-I/F mode, the front porch period continues after displaying one frame data until the next
VSYNC signal input.
8. In the RGB-I/F mode, the data must be written in the high-speed write mode (HWM = 1).
9. In the RGB-I/F mode, the address is set every frame on the falling edge of VSYNC.
From Internal clock operation to RGB I/F (1)
From RGB I/F (1) to Internal clock operation
Internal clock operation
HWM = 1, AM = 0
Set Address
RGB I/F Setting
(DM1-0=01, RM=1)
Index resister
setting (R202h)
Wait more than 1 frame
Display operation
in synchronization with
the internal clock
The settings in DM1-0, RM
become valid after displaying
one frame.
RGB I/F operation
Internal clock mode setting
(DM1-0 = 00, RM=0)
Wait more than 1 frame
Internal clock operation
Display operation in
synchronization
with VSYNC, HSYNC, DOTCLK
The settings in DM1-0, RM
become valid after displaying
one frame.
Display operation
in synchronization with
the internal clock
Note: RGB interface signals must be supplied for at least one frame
when switching to the internal clock operation.
RGB I/F
Write RAM data
RGB interface operation
Display operation in
synchronization
with VSYNC, HSYNC, DOTCLK
Note: RGB interface signals must be supplied before setting DM1-0, RM
when switching to the RGB I/F mode.
Rev.0.5, July.31.2003, page 147 of 196