HD66781 Datasheet, PDF (149/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
The display synchronizing data transfer mode has limits on the minimum speed for RAM write through the
system interface and the frequency of the internal clock. It requires RAM write speed more than the
calculated result from the following formula.
Internal clock frequency (fosc) [Hz]
= Frame frequency × (Display raster-row (NL) + Front porch (FP) +Back porch (BP)) × 16 clocks
× Fluctuation
RAM writing speed (min.) [Hz]
> 320× Display lines (NL)/{[(Front porch (FP)+Back porch (BP)+Display lines (NL) – margin) x 16 clocks] /fosc}
When RAM write does not start immediately after the rising edge of BST, the period from the rising edge
of BST to the start of RAM write must also be taken into consideration.
An example of calculations for the internal clock frequency and RAM write speed in the display
synchronizing data transfer mode is as follows.
• Calculation Example: moving picture display in VSYNC I/F
• Panel size
240 RGB × 320 raster-rows (NL0 = 6’27)
• Total number of raster-rows(NL)
320 raster-rows
• Back, Front porches
14, 2, raster-rows
(BP = 4’hE, FP = 4’h2)
• Frame frequency
60Hz
Internal clock frequency (fosc) Hz
= 60 Hz × (320 + 2 + 14) raster-rows × 16 clocks × 1.1 / 0.9 = 394 [kHz]
When calculating an internal clock frequency, possible causes of fluctuations must also be taken into
consideration. The allowance for this fluctuation is ± 10 % from the center value, and the range of the
frequency must be within the BST signal cycle.
As the causes of fluctuations, the above example takes the variation in the LSI fabrication and the room
temperature into account. Other possible causes of fluctuations, such as variation in the external resistors
or the voltage change are not considered in the above calculation. It is necessary to make a setting with
enough margins to include the allowances for these factors.
Minimum RAM writing speed [Hz]
> 240 × 320 / {((2+14 + 320 - 2) raster-rows × 16 clocks) / 394 kHz} = 5.66 [MHz]
In this case, RAM write is performed on the rising edge of BST.
When the data for one frame are written to RAM completely, there must be 2 raster-rows or more of a
margin before the display raster-rows.
According to the above calculation results, writing data to RAM on the rising of BST at the speed of 5.66
MHz or more, the data for the entire screen on RAM are overwritten before the display operation starts.
Accordingly, the flicker due to moving picture update can be avoided even if displaying a moving picture.
Rev.0.5, July.31.2003, page 149 of 196