HD66781 Datasheet, PDF (47/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Display Control 3 (R009h)
Preliminary
R/W RS
W1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
0 0 0 0 0 PTS2 PTS1 PTS0 0 0 PTG1 PTG0 ISC3 ISC2 ISC1 ISC0
ISC [3:0]: Specify the cycle to scan gate lines, when PTG bits set the scan mode in the non-display area to
the interval scan mode. The scan cycle is always odd number of frames, and polarity inversion is applied
each timing when gate lines are scanned.
Table 22
ISC [3:0]
4’h0
4’h1
4’h2
4’h3
4’h4
4’h5
4’h6
4’h7
4’h8
4’h9
4’hA
4’hB
4’hC
4’hD
4’hE
4’hF
Scan cycle
Setting disabled
3 frames
5 frames
7 frames
9 frames
11 frames
13 frames
15 frames
17 frames
19 frames
21 frames
23 frames
25 frames
27 frames
29 frames
31 frames
When (fFLM) = 60Hz
-
50ms
84ms
117ms
150ms
184ms
217ms
251ms
284ns
317ms
351ms
384ms
418ms
451ms
484ms
518ms
PTG [1:0]: Set the DISPTMG output to determine the gate bus line scan mode in non-display area. The
setting is applied to all no-display areas and front/back porch periods of the entire panel.
Table 23
PTG[1:0]
DISPTMG output
Gate output in non-
display area
2’h0
Normal drive
Normal scan
2’h1
GND
VGL (fixed)
2’h2
Interval drive
Interval scan
2’h3
Setting disabled
-
Note 1) Set alternating drive to frame cycle when using interval scan.
Source output in non-
display area
PT setting
PT setting
PT setting
-
Rev.0.5, July.31.2003, page 47 of 196