HD66781 Datasheet, PDF (21/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
Block Function
(1) System interface
The HD66781 has 2 kinds of high-speed system interfaces: 80-system 18-/16-/9-/8-bit bus interfaces and
Serial Peripheral Interface (SPI) ports. The 8-bit bus interface is compliant to both big and little endian
data outputs from the microcomputer. The interface mode is selected with the IM3-0 pins.
The HD66781 incorporates 16-bit index register (IR), write-data register (WDR), and 16-bit read-data
register (RDR). The IR stores index information from the control register and GRAM. The WDR
temporarily stores data to write into the control register and GRAM, and the RDR temporarily stores data
read from GRAM. Data written into GRAM from MPU is first written into the WDR and then
automatically written to GRAM by internal operation. Since data are read through the RDR from GRAM,
the data that are read out first are invalid and the ensuing data are read out normally.
The execution time for the instructions other than oscillation start is 0-clock cycle, which enables writing
instructions consecutively.
Table 1 Register Selection (8/9/16/18 parallel interface)
80-system bus
WR* RD* RS
0
1
0
1
0
0
0
1
1
1
0
1
Operation
Write index to IR.
Read internal status
Write to control registers/GRAM through WDR
Read from GRAM through RDR
Table 2 Register Selection (SPI)
Start byte
RW
RS
0
0
1
0
0
0
1
1
Operation
Write index to IR.
Read internal status
Write to control registers/GRAM through WDR
Read from GRAM through RDR
Rev.0.5, July.31.2003, page 21 of 196