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| HD66781 Datasheet, PDF (127/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM | |||
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HD66781
Preliminary
(a) Clock synchronization serial transmission (Basic)
Transmission start
Transmission end
CS
input
SCL
input
SDI
input
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MSB
LSB
â0â â1â â1â â1â â0â ID RS RW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Device ID code
RS RW
Start bite
Index register set, instruction set,
RAM data write
SDO
output
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Status read, instruction read, RAM data read
(b) Clock synchronization serial transmission (consecutive)
CS
input
SCL
input
SDI
input
Start
Start bite
Instruction(1)
Upper 8 bits
Instruction(1)
Lower 8 bits
Instruction(2)
Upper 8 bits
Instruction(2)
Lower 8 bits
End
The first bite right after start bite is always upper 8 bits
Instruction (1)
execution time
(c) RAM read-out transmission
CS
input
SCL
input
SDI
input
Start bite
RS=1
R/W=1
SDO
output
Start
dummy read
1
dummy read
2
dummy read
3
dummy read
4
dummy read
5
RAM read
Upper 8 bits
RAM read
Lower 8 bits
End
The 5 bites right after start bite are dummy read, and invalid data are read out to RAM.
Normal RAM data read starts from the 6th byte.
(d) status read, instruction read
CS
input
SCL
input
SDI
input
SDO
output
Start
Start byte
RS = 0
R/W = 1
dummy read
1
Status Read
Upper 8 bits
Status Read
Lower 8 bits
The 1 bite right after Start bite is dummy, and invalid data are read out
End
to RAM. Normal RAM data read starts from the 2nd byte.
Serial Peripheral Interface: data transfer
Rev.0.5, July.31.2003, page 127 of 196
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