HD66781 Datasheet, PDF (64/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Gate Driver/LTPS LCD Panel Interface Control 9 (R019h)
Preliminary
R/W RS
W1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
DPW DPW DPW DPW DPW DPW
0 0 _{E5 E4 E3 E2 E1 E0} 0 0
00
DPTE DPTE DPTE
02 _{1 0}
DPTE[2:0]: Specify the rising position of DISPTMG during display operation with DOTCLK (DM =
2’h1).
DPWE[5:0]: DPWE specifies the width of “High” of DISPTMG during display operation with DOTCLK
(DM = 2’h1) when LTPS = 1. The register setting is invalid when LTPS = 0. In this case, the falling
position of CL1 is at a reference point.
See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD
panel interface are controlled by these settings.
Table 42
DPTE[2:0] DISPTMG Rising position
DPWE[5:0] DISPTMG “High” width
3’h0
0 clock
6’h00
0 clock
3’h1
1 clock
6’h01
1 clock
3’h2
2 clocks
6’h02
2 clocks
3’h3
3 clocks
6’h03
3 clocks
3’h4
4 clocks
:
:
3’h5
5 clocks
6’h3D
61 clocks
3’h6
6 clocks
6’h3E
62 clocks
3’h7
7 clocks
6’h3F
63 clocks
Note 1) The clocks in the tables are DOTCLK / division ratio for the 1H period, measured from a reference
point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is
set to 0 clock.
Note 2) The gate non-overlap period can be set to 0 when DPTI = “2’h0” and DPWI is set to the number of
clocks more than that of the 1H period.
Rev.0.5, July.31.2003, page 64 of 196