HD66781 Datasheet, PDF (20/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

GND
1uF/3V/B
1.7~3.3V
Vcc1(781)=VCC(7P21)
1.7~3.3V
IOVcc
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
ENABLE
DOTCLK
HSYNC
VSYNC
DACK*
CS*
RS
WR*/SCL
RD*
DB0/SDI
DB1/SDO
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
BST
RESET*
SIN7
VF<0.4V/20mA at 25 , VR 30V
Vcc(781)=Vci(7P21)
2.5 3.3V
1uF/6V/B
> 200kW
1uF/6V/B
1uF/10V/B
VF<0.4V/20mA at 25 , VR 30V
1uF/25V/B
1uF/25V/B
1uF/6V/B
1uF/6V/B
1uF/6V/B
VF<0.4V/20mA at 25 , VR 30V
1uF/25V/B
1uF/25V/B
1uF/6V/B
1uF/6V/B
1uF/10V/B
1uF/10V/B
80-system 18-bit
interface
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
10ohm 1
1
1
1
1
1
1
1
10ohm 1
1
1
1
1
1
1
1
5ohm
1
1
1
1
1
1
1
20ohm
1
1
1
1
1
1
1
1
1
1
5ohm 1
1
1
1
1
1
1
1
1
1
1
1
10ohm 1
1
1
1
1
1
20ohm
1
1
1
1
20
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DUMMY17
TESTO2
DUMMY16
DUMMY15
DUMMY14
DUMMY13
DUMMY12
TVcc2
TVcc1
AGNDDUM4
TOUT3
TOUT2
TOUT1
TIN1
AGNDDUM3
FLM2
SFTCLK22
CL12/SFTCLK12
M2
EQ2
DISPTMG2
GDA2
GCS2*
GCL2
DCCLK2
RESETO2
TS0
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
TEST2
TEST1
AGNDDUM2
IM3
IM2
IM1
IM0/ID
IOVccDUM3
OSC3
Vcc1DUM2
DUMMY11
OSC2
DUMMY10
DUMMY9
OSC1
DUMMY8
AGNDDUM1
TSC
DUMMY7
VDDTEST
VREFC2
VREFC1
DUMMY6
VREF
VRTEST
VREFD
DUMMY5
Vcom
Vcom
VTEST
VMON
PMON
VDH
VGS
V63N
V63P
V0N
V0P
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
GND
GND
GND
GND
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc1
Vcc1
Vcc1
Vcc1
IOVcc
IOVcc
IOVcc
IOVcc
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
ENABLE
DOTCLK
HSYNC
VSYNC
Vcc1DUM1
DACK*
DUMMY4
CS*
RS
WR*/SCL
RD*
IOVccDUM2
DB0/SDI
DB1/SDO
DB2
DB3
DB4
DB5
DB6
DB7
DB8
IOVccDUM1
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
DUMMY3
BST
RESET*
DUMMY2
RESETO1
DCCLK1
GCL1
GCS1*
GDA1
DISPTMG1
EQ1
M1
CL11/SFTCLK11
SFTCLK21
FLM1
TESTO1
DUMMY1
Short-circuit DUMMY14
and DUMMY15
within LSI
Laced
Output
1
1
1
1
1
1
1
1
1 DUMMY22
1 DUMMY23
1 S643
1 S642
Source Electrode
1 S79
1 S78
1 DUMMY25
1 DUMMY26
Example of connecting
HD66781 and HD667P21
Poly-Si TFT
IOVcc = 1.7V~3.3V (HD66781)
Vcc1 = 1.7~3.3V (HD66781)
Vcc = 2.5~3.3V (HD66781)
VCC = 1.7~3.3V (HD667P21)
VCI = 2.5~3.3V (HD667P21)
Supply a same potential to Vcc1 of HD66781 and VCC of HD667P21.
Make sure that IOVcc Vcc1 Vcc (HD66781).
DMY4 1
Fix to GND
111111111111111111111
1 DMY7
1
1
1
5ohm 1
1
1
10ohm 1
1
1
1
1
5ohm 1
1
1
1
10ohm 1
1
1
40ohm 1
1
1
10ohm 1
1
1
40ohm 1
1
1
50ohm 1
1
20ohm 1
1
20ohm 1
1
40ohm 1
1
1
20ohm 1
1
30~50ohm 1
1
1
10ohm ¹
1
1
1
1
10ohm 1
1
1
20ohm 1
1
1
20ohm 1
1
40ohm ¹
1
40ohm ¹
1
40ohm ¹
1
40ohm ¹
1
1
DMY3
Vci
Vci
Vci
Vci
Vci
VCC
VCC
GND
GND
GND
GND
GND
GND
VciOUT
Vci1
Vci1
VCOMR
VREG1
VREG1OUT
VLOUT1
DDVDH
DDVDH
DDVDH
VLOUT2
VLOUT2
VGH
VGH
VCOMH
VCOMH
VCOML
VCOML
VCL
VCL
VLOUT4
VLOUT3
VLOUT3
VLOUT3
VGL
VGL
C11-
C11-
C11-
C11-
C11+
C11+
C11+
C11+
C12-
C12-
C12-
C12+
C12+
C12+
C21-
C21-
C21+
C21+
C22-
C22-
C22+
C22+
DMY2
DMY8 1
DMY9 1
DMY10 1
DMY11 1
DMY12 1
GNDDMY3 1
GNDDMY4 1
GNDDMY5 1
TESTM 1
TESTL 1
TESTG 1
VCCDMY2 1
VCCDMY3 1
VTEST 1
SOUT8 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Vcom 1
Vcom 1
CLCO 1
CLBO 1
CLAO 1
SOUT7 1
SOUT6 1
SOUT5 1
SOUT4 1
SOUT3 1
SOUT2 1
SOUT1 1
SOUT1 1
DMY30 1
DMY31 1
DMY32 1
DMY33 1
DMY34 1
DMY 1
1111111111111111111111
1 DMY35
To opposing electrodes on the panel(Vcom)
Gate Circuit
Bottom View (Non Bump View)
Chip
Glass