HD66781 Datasheet, PDF (56/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
HSPL: Specify the polarities of signals on HSYNC pin.
HSPL=0: Low active.
HSPL=1: High active.
VSPL: Specify the polarities of signals on VSYNC pin.
VSPL=0: Low active.
VSPL=1: High active.
Preliminary
Gate Driver/LTPS LCD Panel Interface Control 1 (R010h)
R/W RS
W1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
0
FWI FWI FWI FWI FWI
0 0 ₄₃
210
0
0
00
0 FTI2 FTI1 FTI0
FTI[2:0]: FTI bits specify the rising position of FLM during display operation with internal clocks (DM =
2’h0 or 2’h2) when LTPS = 1. The setting of this register is invalid when LTPS = 0. In this case, the rising
position of FLM is at a reference point.
FWI[4:0]: FWI bits specifies the width of “High” of FLM during display operation with internal clocks
(DM = 2’h0 or 2’h2) when LTPS = 1. The setting of this register is invalid when LTPS = 0. In this case,
the width of “High” of FLM is 1H.
See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD
panel interface are controlled by these settings.
Table 34
FTI[2:0] FLM Rising position
FWI[4:0] FLM “High” width
2’h0
0 clock
5’h00
0 clock
2’h1
1 clock
5’h01
1 clock
2’h2
2 clocks
5’h02
2 clocks
2’h3
3 clocks
5’h03
3 clocks
:
:
5’h1D
29 clocks
5’h1E
30 clocks
5’h1F
31 clocks
Note 1) The clocks in the tables are measured from the reference point. The reference point is the position
where SFTCLK rises when the rising position of SFTCLK is set to 0 clock.
Rev.0.5, July.31.2003, page 56 of 196