HD66781 Datasheet, PDF (55/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
External Display Interface Control 2 (R00Eh)
Preliminary
R/W RS
W1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
DIVE DIVE
RTNE RTNE RTNE RTNERTNE RTNE RTNE
000000
10
0 ₆₅
4 32 1 0
RTNE[6:0]: Specify the number of clocks for internal operation per 1H (line). Set the value of the number
of DOTCLK input in 1H period, divided by the division ratio.
DIVE[1:0]: Set the internal division ratio of DOTCLK (DIVE). The internal operation is executed
according to the clocks divided by the division ratio set by DIVE.
Table 33
RTNE[6:0]
7’h00
:
7’h0F
7’h10
7’h11
7’h12
:
7’h7D
7’h7E
7’h7F
Clocks per line
Setting disabled
:
Setting disabled
16 clocks
17 clocks
18 clocks
:
125 clocks
126 clocks
127 clocks
DIVE[1:0] Division Internal operation clock frequency
2’h0
Setting disabled
2’h1
1/4
fdotclk / 4
2’h2
1/8
fdotclk / 8
2’h3
1/16
fdotclk / 16
fdotclk: DOTCLK frequency
External Display Interface Control 3 (R00Fh)
R/W RS
W1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
0 0 0 0 0 0 0 0 0 0 0 ^{VSPL HSPL 0 EPL DPL}
DPL: Specify the polarities of signals on DOTCLK pin.
DPL=0: Input data on a rising edge of DOTCLK.
DPL=1: Input data on a falling edge of DOTCLK.
EPL: Specify the polarities of signals on ENABLE pin.
EDL = 0
EDL = 1
Data are written to PD17 to PD 0 when ENABLE = 0. No data are written when
ENABLE = 1.
Data are written to PD17 to PD 0 when ENABLE = 1. No data are written when
ENABLE = 0.
Rev.0.5, July.31.2003, page 55 of 196